And the fact that logic takes so long to synthesize and simulate really has little to do with Verilog's deficiencies; if anything it's a limitation of the register-transfer level abstraction that's currently used to design digital hardware.
If that's the case, then why are Chisel and bluespec much faster to simulate despite having less investment in tooling?
If that's the case, then why are Chisel and bluespec much faster to simulate despite having less investment in tooling?